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期刊論文
  1. Hsu-Yu Kao; Shih-Hsu Huang; Wei-Kai Cheng , “Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware Evaluation” , 2022 , Electronics , vol.11 , p.2107:1-2107:17. (SCI期刊)
  2. Yui-Kai Weng; Shih-Hsu Huang; Hsu-Yu Kao , “Block-Based Compression and Corresponding Hardware Circuits for Sparse Activations” , 2021 , Sensors , vol.21 , p.7468:1-7468:15. (SCI期刊)
  3. Hsu-Yu Kao; Xin-Jia Chen; Shih-Hsu Huang , “Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing” , 2021 , Sensors , vol.21 , p.5081:1-5081:19. (SCI期刊)
  4. 董哲瑋 ; 黃世旭 , “A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process” , 2020 , IEEE Access , vol.8 , p.87367-87377. (SCI期刊)
  5. Chung-Han Chou; Yen-Ting Lai; Yi-Chun Chang; Chih-Yu Wang; Shih-Hsu Huang; Shih-Chieh Chang , “Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction” , 2017 , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , vol.36 , p.146-155. (SCI期刊)
  6. 鄭維壬;程駿華;黃世旭 , “可靠度導向時鐘選擇之高階合成方法” , 2016 , 先進工程學刊 , vol.11 , p.287-294. (華藝線上圖書館期刊)
  7. Shih-Hsu Huang, Chun-Hua Cheng , “Power-Mode-Aware Buffer Synthesis for Low-Power Clock Skew Minimization” , 2016 , IEICE Electronics Express (ELEX) , vol.13 , p.1-12. (SCI期刊)
  8. Shih-Hsu Huang, Ching-Chun Chiu, Chun-Hua Cheng, Te-Jui Wang , “Simultaneous Test Scheduling and TAM Bus Wire Assignment for Temperature-Dependent Core-Based SoC Testing” , 2016 , International Journal of Electrical Engineering (IJEE) , vol.23 , p.53-62. (EI期刊)
  9. Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang , “Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs” , 2016 , IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.24 , p.1189-1192. (SCI期刊)
  10. Shih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh , “Clock Period Minimization with Minimum Leakage Power” , 2015 , ACM Transactions on Design Automation of Electronic Systems (TODAES) , vol.21 , p.9:1-9:33. (SCI期刊)
  11. Shih-Hsu Huang; Hua-Hsin Yeh , “Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits” , 2014 , IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences , vol.97-A , p.1699-1708. (SCI期刊)
  12. Shih-Hsu Huang ; Wen-Pin Tu; Chia-Ming Chang; Song-Bin Pan , “Low-Power Anti-Aging Zero Skew Clock Gating” , 2013 , ACM Transactions on Design Automation of Electronic Systems (TODAES) , vol.18 , p.27:1-27:37. (SCI期刊)
  13. Shih-Hsu Huang; Wen-Pin Tu; Bing-Hung Li , “High-Level Synthesis for Minimum-Area Low-Power Clock Gating” , 2012 , Journal of Information Science and Engineering , vol.28 , p.971-988. (SCI期刊)
  14. Shih-Hsu Huang; Guan-Yu Jhuo; Wei-Lun Huang , “Minimum Inserted Buffers for Clock Period Minimization” , 2011 , Journal of Information Science and Engineering , vol.27 , p.1513-1526. (SCI期刊)
  15. Chih-Hung Lee; Shih-Hsu Huang; Chun-Hua Cheng , “Accurate TSV Number Minimization in High-Level Synthesis” , 2011 , Journal of Information Science and Engineering , vol.27 , p.1527-1543.
  16. Shih-Hsu Huang; Chun-Hua Cheng , “Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization” , 2010 , Journal of Information Science and Engineering , vol.26 , p.2249-2266. (SCI期刊)
  17. Shih-Hsu Huang; Chun-Hua Cheng; Da-Chen Tzeng , “Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization” , 2009 , Journal of Information Science and Engineering , vol.25 , p.1707-1722. (SCI期刊)
  18. Shih-Hsu Huang; Chun-Hua Cheng; Song-Bin Pan , “Synthesis of Anti-Aging Gated Clock Designs” , 2009 , Journal of Information Science and Engineering , vol.25 , p.1651-1670. (SCI期刊)
  19. Shih-Hsu Huang; Chun-Hua Cheng , “Minimum-Period Register Binding” , 2009 , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol.28 , p.1265-1269. (SCI期刊)
  20. Shih-Hsu Huang; Jheng-Fu Yeh; Chun-Hua Cheng , “An ILP Approach to Surge Current Minimization in High-Level Synthesis” , 2009 , IEICE Electronics Express , vol.6 , p.979-985. (SCI期刊)
  21. Shih-Hsu Huang; Chia-Ming Chang; Yow-Tyng Nieh , “Opposite-Phase Register Switching for Peak Current Minimization” , 2009 , ACM Ttransactions on Design Automation of Electronic Systems , vol.14 (SCI期刊)
  22. Shih-Hsu Huang; Chun-Hua Cheng , “Power-Management Scheduling for Peak Power Minimization” , 2008 , Journal of Information Science and Engineering , vol.24 , p.1647-1668. (SCI期刊)
  23. Chun-Hua Cheng; Shih-Hsu Huang; Wen-Pin Tu , “Module Binding for Low Power Clock Gating” , 2008 , IEICE Electronics Express , vol.5 , p.762-768. (SCI期刊)
  24. Wei-Chieh Yu; Shih-Hsu Huang , “An ILP Approach to Heat Driven Functional Unit Binding” , 2008 , Tamkang Journal of Science and Engineering , vol.11 , p.29-36. (EI期刊)
  25. Shih-Hsu Huang; Chun-Hua Cheng , “An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management” , 2008 , IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences , vol.E91-A , p.375-382. (SCI期刊)
  26. Yow-Tyng Nieh; Shih-Hsu Huang; Sheng-Yu Hsu , “Opposite-Phase Clock Tree for Peak Current Reduction” , 2007 , IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences , vol.90-A (SCI期刊)
  27. Shih-Hsu Huang; Chia-Ming Chang; Yow-Tyng Nieh, , “A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains” , 2007 , Journal of Information Science and Engineering (JISE) , vol.23 (SCI期刊)
  28. Shih-Hsu Huang; Chun-Hua Cheng , “Operation Scheduling for the Synthesis of False Loop Free Circuits” , 2007 , IEICE Electronics Express (ELEX) , vol.4 (SCI期刊)
  29. Shih-Hsu Huang; Yow-Tyng Nieh, , “Clock Skew Scheduling with Race Conditions Considered” , 2007 , ACM Transactions on Design Automation of Electronic Systems (TODAES) , vol.12 (SCI期刊)
  30. 黃世旭, 聶佑庭 , “Synthesis of Nonzero Clock Skew Circuits” , 2006 , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , vol.25 , p.961-976. (SCI期刊)
  31. 黃世旭, 程駿華 , “An ILP Approach to the Slack Driven Schedulin Problem” , 2006 , IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences , vol.89-A , p.1852-1858. (SCI期刊)
  32. 黃世旭, 賴建元 , “A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities” , 2005 , IEICE Transactions on Information and Systems , vol.88-D , p.2410-2416. (SCI期刊)
  33. 黃世旭, 聶佑庭, 呂逢彬 , “Clock Tree Optimization for the Tolerance of Process Variation” , 2005 , 中原學報 , vol.33 , p.513-518.
  34. 黃世旭, 賴建元 , “A High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions” , 2005 , Journal of Information Science and Engineering , vol.21 , p.607-626. (SCI期刊)
  35. 陳奕融, 黃世旭 , “Design and Simulation of Type-2 Fuzzy Inference Processor” , 2004 , Journal of Technology , vol.19 , p.317-326.
  36. S.H. Huang, Y.T. Nieh and C.L. Wang , “An Effective Approach to Designing a Power Distribution Network at the Post-Floorplan Stage” , 2004 , International Journal of Electrical Engineering , vol.11 , p.407-416. (EI期刊)
  37. S.H. Huang, W.H. Peng, S.Z. Lin and J.Y. Lai , “Design Automation of Fuzzy Rules Based on Trapezoid-Shaped Membership Functions” , 2004 , Chung Yuan Journal (中原學報) , vol.32 , p.383-392.
  38. S.H. Huang, Y.T. Nieh and Y.H. Lin , “Performance and Power Driven Non-Zero Skew Clock Tree Design Methodology” , 2004 , Chung Yuan Journal , vol.32
  39. S.H. Huang, Y.S. Hsu and C.C. Lin , “A Timing Driven Crosstalk Optimizer for Gridded Channel Routing” , 2004 , IEICE Transactions on Information and Systems , vol.87-D , p.1575-1581. (SCI期刊)
  40. 黃世旭, 劉時誌 , “以最小成本實現最佳非零時序差異排序的時鐘樹設計方法” , 2003 , 中原學報 , vol.31 , p.221-231.
  41. 黃世旭 , “考慮接線效應之深次微米晶片設計流程及設計方法” , 2003 , Engineering Science & Technology Bulletin, NSC , vol.67 , p.58-62.
  42. 黃世旭 , 許益祥 , “降低串音效應造成之時間延遲的通道繞線演算法” , 2002 , 中原學報 , vol.30 , p.377-383.
  43. S.H. Huang, Mely Chen Chi, H.M. Hsiao , “A Practical Interconnect-Driven Design Methodology For Low Power ASIC Designs” , 2001 , Chung Yuan Journal , vol.0 , p.93-101.
  44. Siih-Hsu Huang, Jian-Yuan Lai , “An Efficient Membership Function Representation For High-Resolution Fuzzy Systems” , 2001 , Chung Yuan Journal , vol.29 , p.285-291.
  45. M.C. Chi and S.H. Huang , “A Reliable Clock Tree Design Methodology for ASIC Designs” , 2000 , Chung Yuan Journal , vol.28 , p.115-122.
  46. 黃世旭 , “A Design Methodology for a 0.35um IC Project” , 1999 , CCL Technical Journal , vol.0
  47. S.H. Huang, K.C. Jung, C.H. Kao, Mely Chen Chi , “Precise SDF Files Generation for Clock Trees” , 1997 , TechnicalJournalofComputer&CommunicationsResearchLaboratories , vol.62 , p.32-39.
  48. J.M. Tseng, S.H. Huang, C.Y. Lee, Mely Chen Chi , “The Creation and Application of Wire Load Model in ASIC Design” , 1997 , Technical Journal of Computer & Communications Research Laboratories , vol.62 , p.21-27.
  49. C.Y. Lee, Y.R. Lin, Mely Chen Chi, S.H. Huang, K.C. Jung , “Clock Tree Synthesis Flow” , 1997 , Technical Journal of Computer & Communications Research Laboratories , vol.62 , p.28-31.
  50. S.H. Huang, K.C. Jung, Y.R. Lin, J.Y. Tseng, C.H. Chien , “Links-to-Layout Design Environment” , 1996 , Technical Journal of Computer & Communications Research Laboratories , vol.52 , p.30-38.
  51. S.H. Huang, C.T. Tseng, Y.C. Hsu, Y.J. Oyang , “A New Approach to Schedule Operations across Nested-ifs and Nested-loops” , 1995 , EuroMicro Journal: Microprocessing and Microprogramming , vol.41 , p.37-52. (SCI期刊)
  52. S.H. Huang, Y.C. Hsu, Y.J. Oyang , “A New Scheduling Algorithm for Synthesizing the Control Blocks of Control-Dominated Circuits” , 1995 , EuroMicro Journal: Microprocessing and Microprogramming , vol.41 , p.501-519. (SCI期刊)
  53. S.H. Huang , “The Design Environment of High-Level Synthesis” , 1995 , Technical Journal of Computer & Communications Research Laboratories , vol.42 , p.37-48.
研討會論文
  1. Yung-Chieh Lin; Shih-Hsu Huang , “An Approximate Fault-Tolerance Mechanism for SRAM-Based Near-Memory MAC Units” , 2024 , Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) , 2024 /3 /11 ~ 2024 /3 /12 , 中華民國 台灣 .
  2. Shih-Hsu Huang; Wei-Che Cheng; Jin-Fu Li , “Hardware Trojans of Computing-In-Memories: Issues and Methods” , 2023 , IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems , 2023 /10 /3 ~ 2023 /10 /5 , France .
  3. Chia-Jo Lin; Shih-Hsu Huang; Wan-Yi Hsueh; Wei-Chung Hsu; Chih-Wen Su , “An Automatic Facial Analysis System for The Detection of Obstructive Sleep Apnea” , 2023 , IEEE ICCE-TW 2023 , 2023 /7 /17 ~ 2023 /7 /19 , 中華民國 台灣 .
  4. Hsin-Chen Lu;Shin-Hsu Huang , “Fault-Tolerant Near-Memory MAC Design with Redundant Memories” , 2023 , IEEE ICCE-TW 2023 , 2023 /7 /17 ~ 2023 /7 /19 , 中華民國 台灣 .
  5. Liang-Ying Su;Shin-Hsu Huang , “A metal-Only ECO Algorithm for Improving Hardware Security with Gate Camouflaging” , 2023 , IEEE ICCE-TW 2023 , 2023 /7 /17 ~ 2023 /7 /19 , 中華民國 台灣 .
  6. 黃世旭 , “A Survey on Hardware Security Techniques for Preventing Reverse Engineering Attacks” , 2023 , 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA) , 2023 /4 /17 ~ 2023 /4 /20 , 中華民國 台灣 .
  7. Yi-Ren Chen; Shih-Hsu Huang , “Design Flow for The Implementation of Obfuscated Finite State Machines” , 2022 , IET International Conference on Engineering Technologies and Applications , 2022 /10 /14 ~ 2022 /10 /16 , 中華民國 台灣 .
  8. Chuan-Han Cheng;Shih-Hsu Huang;Jin-Fu Li , “Design and Dataflow for Multibit SRAM-Based MAC Operations” , 2022 , 2022 19th International SoC Design Conference , 2022 /10 /19 ~ 2022 /10 /19 , 中華民國 台灣 .
  9. Yi-Ren Chen;Shih-Hsu Huang , “Design Flow for The Implement of Obfuscated Finite State Machines” , 2022 , IET ICETA 2022 , 2022 /10 /14 ~ 2022 /10 /16 , 中華民國 台灣 .
  10. De-Yang Chiu;Shih-Hsu Huang , “Network Pruning by Feature Map Sharing with K-Means Clustering” , 2022 , IEEE ICCE-Taiwan 2022 , 2022 /7 /6 ~ 2022 /7 /8 , 中華民國 台灣 .
  11. Bo-Xi Lai;Shih-Hsu Huang;Hsu-Yu Kao , “A Reinforcement Learning Methodology for The Search of SRAM CIM-based Accelerator Configuration” , 2022 , 2022 IEEE ICCE-Taiwan , 2022 /7 /6 ~ 2022 /7 /8 , 中華民國 台灣 .
  12. Jia-Xiang Tang;Shih-Hsu Huang;Jui-Hung Hung , “ECO Timing Optimization with Data Paths and Clock Paths Considered” , 2021 , 2021 ISPACS , 2021 /11 /16 ~ 2021 /11 /19 , 中華民國 台灣 .
  13. Yui-Kai Weng;Shih-Hsu Huang;Hsu-Yu Kao , “Block-Based Compression for Reducing Indexing Cost of DNN Accelerators” , 2021 , 2021 IEEE ICCE-TW PENGHU , 2021 /6 /16 ~ 2021 /6 /18 , 中華民國 台灣 .
  14. Yi-Liang Hong;Yui-Kai Weng;Shih-Hsu Huang , “Hardware Implementation for Fending off Side-Channel Attacks” , 2021 , 2021 IEEE ICCE-TW PENGHU , 2021 /6 /16 ~ 2021 /6 /18 , 中華民國 台灣 .
  15. En-Hui Zhang; Shih-Hsu Huang , “Low-Power Low-Error FixedWidth Multiplier Design for Digital Signal Processing” , 2021 , IEEE International Conference on Consumer Electronics (ICCE) , 2021 /1 /10 ~ 2021 /1 /12 , United States .
  16. Yu-Hsuan Wu;Wei-Hung Lin;Shih-Hsu Huang , “Low-Power Hardware Implementation for Parametric Rectified Linear Unit Function” , 2020 , IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW) , 2020 /9 /28 ~ 2020 /9 /30 , 中華民國 台灣 .
  17. Xin-Jia Chen;Shih-Hsu Huang , “Low-power Small-Area 3x3 Convolution Hardware Design” , 2020 , IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW) , 2020 /9 /28 ~ 2020 /9 /30 , 中華民國 台灣 .
  18. Shi-Rou Lin;Wei-Hung Lin;Shih-Hsu Huang , “Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design” , 2020 , IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW) , 2020 /9 /28 ~ 2020 /9 /30 , 中華民國 台灣 .
  19. En-Hui Zhang; Shih-Hsu Huang , “A Simple Yet Accurate Method for The Unsigned Fixed-Width Multiplier Design” , 2020 , IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW) , 2020 /9 /28 ~ 2020 /9 /30 , 中華民國 台灣 .
  20. 劉哲宏;黃世旭 , “於FPGA使用近似乘法實現YOLO-v2神經網路模型” , 2020 , 2020 第十四屆積體光機電科技與智慧財產實務研討會 , 2020 /5 /27 ~ 2020 /5 /27 , 中華民國 台灣 .
  21. 洪瑞鴻 ; 黃世旭 ; 程駿華 ; 高勗宥 ; 鄭維凱 , “Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers” , 2020 , IEEE VLSI Test Symposium (VTS) , 2020 /4 /27 ~ 2020 /4 /30 , United States .
  22. 林威宏 ; 高勗宥 ; 黃世旭 , “A Design Framework for Hardware Approximation of Deep Neural Networks” , 2019 , IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) , 2019 /12 /3 ~ 2019 /12 /6 , 中華民國 台灣 .
  23. 張智翔; 張恩惠; 黃世旭 , “Softsign Function Hardware Implementation Using Piecewise Linear Approximation” , 2019 , IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) , 2019 /12 /3 ~ 2019 /12 /6 , 中華民國 台灣 .
  24. 唐汎瑄 ; 高勗宥 ; 黃世旭; 李進福 , “3D Test Wrapper Chain Optimization with I/O Cells Binding Considered” , 2019 , IEEE International 3D Systems Integration Conference (3DIC) , 2019 /10 /8 ~ 2019 /10 /10 , Japan .
  25. 楊維軒 ; 李進福 ; 許鈞瓏 ; 孫際恬 ; 黃世旭 , “A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs” , 2019 , IEEE International 3D Systems Integration Conference (3DIC) , 2019 /10 /8 ~ 2019 /10 /10 , Japan .
  26. 唐汎瑄;高勗宥;黃世旭 , “考慮掃描鍊與輸出入元件綁定關係之積體電路測試包裝鍊優化” , 2019 , 數位生活科技研討會 , 2019 /6 /22 ~ 2019 /6 /23 , 中華民國 台灣 .
  27. Chih-Hsiang Chang; Hsu-Yu Kao; Shih-Hsu Huang , “Hardware Implementation for Multiple Activation Functions” , 2019 , IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW) , 2019 /5 /20 ~ 2019 /5 /22 , 中華民國 台灣 .
  28. Po-Chieh Chang; Shih-Hsu Huang , “ IC Camouflaging by Using Universal Gates under Timing Constraints” , 2019 , IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW) , 2019 /5 /20 ~ 2019 /5 /22 , 中華民國 台灣 .
  29. Che-Wei Tung; Shih-Hsu Huang , “Low-Power High-Accuracy Approximate Multiplier Using Approximate High-Order Compressors” , 2019 , IEEE International Conference on Communication Engineering and Technology (ICCET) , 2019 /4 /12 ~ 2019 /4 /15 , Japan .
  30. Hsu-Yu Kao; Chu-Han Hsu; Shih-Hsu Huang , “Two-Stage Multi-bit Flip-Flop Clustering with Useful Skew for Low Power” , 2019 , IEEE International Conference on Communication Engineering and Technology (ICCET) , 2019 /4 /12 ~ 2019 /4 /15 , Japan .
  31. Chen-Hsien Lin; Shih-Hsu Huang; Wei-Kai Cheng , “An Effective Approach for Building Low-Power General Activity-Driven Clock Trees” , 2018 , IEEE International SoC Design Conference (ISOCC) , 2018 /11 /12 ~ 2018 /11 /15 , Republic of Korea .
  32. Wei-Kai Cheng; Jian-Kai Chen; Shih-Hsu Huang , “Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction” , 2018 , IEEE International SoC Design Conference (ISOCC) , 2018 /11 /12 ~ 2018 /11 /15 , Republic of Korea .
  33. Zong-Han Xie ; Shih-Hsu Huang ; Chun-Hua Cheng , “Utilizing Power Management and Timing Slack for Low Power in High-Level Synthesis” , 2018 , IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW) , 2018 /5 /19 ~ 2018 /5 /21 , 中華民國 台灣 .
  34. Yu-Yi Wu ; Shih-Hsu Huang , “TSV-Aware 3D Test Wrapper Chain Optimization” , 2018 , IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) , 2018 /4 /16 ~ 2018 /4 /19 , 中華民國 台灣 .
  35. Myung-Chul Kim; Shih-Hsu Huang; Rung-Bin Lin; Shigetoshi Nakatake , “Overview of the 2017 CAD Contest at ICCAD” , 2017 , IEEE International Conference on Computer-Aided Design (ICCAD) , 2017 /11 /13 ~ 2017 /11 /16 , United States .
  36. Yen-Chun Ko; Shih-Hsu Huang , “3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints” , 2017 , IEEE Asian Test Symposium (ATS) , 2017 /11 /27 ~ 2017 /11 /30 , 中華民國 台灣 .
  37. Yu Lee; Shih-Hsu Huang , “On-chip-variation-aware Power-mode-aware Buffer Synthesis for Clock Skew Minimization” , 2017 , IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) , 2017 /10 /18 ~ 2017 /10 /20 , 中華民國 台灣 .
  38. Shun-Cheng Yang; Shih-Hsu Huang , “Non-uniform Clock Mesh Synthesis under Temperature Constraints” , 2017 , IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) , 2017 /10 /18 ~ 2017 /10 /20 , 中華民國 台灣 .
  39. Hsu-Yu Kao;Yu Lee;Shih-Hsu Huang;Wei-Kai Cheng;Yih-Chih Chou , “An Industrial OCV-Aware Top-Level Clock Tree Synthesis Methodology” , 2017 , Design Automation Conference , 2017 /6 /18 ~ 2017 /6 /22 , United States .
  40. 楊舜誠;黃世旭 , “考慮溫度效應之非均勻時鐘網格合成” , 2017 , 2017電子信號與通訊創新科技研討會 , 2017 /5 /26 ~ 2017 /5 /26 , 中華民國 台灣 .
  41. 謝宗翰;程駿華;黃世旭 , “同時運算元排序及運算元延遲選擇之高階合成問題研究” , 2017 , 2017電子信號與通訊創新科技研討會 , 2017 /5 /26 ~ 2017 /5 /26 , 中華民國 台灣 .
  42. Shih-Hsu Huang; Rung-Bin Lin; Myung-Chul Kim; Shigetoshi Nakatake , “Overview of the 2016 CAD Contest at ICCAD” , 2016 , 2016 International Conference on Computer Aided Design (ICCAD) , 2016 /11 /7 ~ 2016 /11 /10 , United States .
  43. Jing-Ren Chen; An-Jie Shih; Chun-Wei Lee; Chun-Hua Cheng; Shih-Hsu Huang , “Layer Assignment for Maximizing The Reliability of 3D ICs” , 2016 , IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT) , 2016 /10 /26 ~ 2016 /10 /28 , 中華民國 台灣 .
  44. Wen-Zen Cheng; Chun-Hua Cheng; Shih-Hsu Huang , “Reliability-Driven High-Level Synthesis with Clock Frequency Considered” , 2016 , IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT) , 2016 /10 /26 ~ 2016 /10 /28 , 中華民國 台灣 .
  45. Shih-Hsu Huang; Jian-Zhi Shen; Chun-Hua Cheng , “Layer Assignment for Multi-Power-Mode 3D IC Designs with Power Distribution Networks Considered” , 2016 , Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) , 2016 /10 /24 ~ 2016 /10 /25 , Japan .
  46. Chang-Han Yeh;Yeh-Chun Ko;Chun-Hua Cheng;Shih-Hsu Huang , “The Assignment of Memory BIST Controllers with Circuit Area and Test Application Time Considered” , 2016 , 第二十七屆超大型積體電路設計暨計算機輔助設計技術研討會 , 2016 /8 /2 ~ 2016 /8 /5 , 中華民國 台灣 .
  47. Ming-Hsuan Hsu; Chun-Hua Cheng; Shih-Hsu Huang , “3D IC Test Scheduling with Test Pads Considered” , 2016 , 2016 International Symposium on Next-Generation Electronics , 2016 /5 /4 ~ 2016 /5 /6 , 中華民國 台灣 .
  48. Chun-Hua Cheng; Shih-Hsu Huang; Tsung-Tang Lin , “Watermark-Strength-Aware Register Binding” , 2016 , IEEE International Symposium on Next-Generation Electronics (ISNE) , 2016 /5 /4 ~ 2016 /5 /6 , 中華民國 台灣 .
  49. Chang-Han Yeh; Chun-Hua Cheng; Shih-Hsu Huang , “Grouping and Placement of Memory BIST Controllers for Test Application Time Minimiztion” , 2016 , 2016 International Symposium on Next-Generation Electronics , 2016 /4 /4 ~ 2016 /4 /6 , 中華民國 台灣 .
  50. Natarajan Viswanathan; Shih-Hsu Huang; Rung-Bin Lin; Myung-Chul Kim , “Overview of the 2015 CAD Contest at ICCAD” , 2015 , 2015 IEEE International Conference on Computer-Aided Design (ICCAD) , 2015 /11 /2 ~ 2015 /11 /6 , United States .
  51. 粘丞勛; 程駿華; 黃世旭 , “經由重新分配測試介面輸入個數以最小化多核心SoC測試時間之研究” , 2015 , 2015第十屆智慧生活科技研討會 , 2015 /6 /5 ~ 2015 /6 /5 , 中華民國 台灣 .
  52. Te-Jui Wang; Ching-Chun Chiu; Shin-Hsu Huang , “Simultaneous Test Scheduling and TAM Bus Wire Assignment for Core-Based SoC Designs” , 2015 , The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies , 2015 /3 /16 ~ 2015 /3 /17 , 中華民國 台灣 .
  53. Tsung-Tang Lin, Wen-Pin Tu, Shih-Hsu Huang , “Self-Adjusting Mechanism to Dynamically Suppress the Effect of PVT Variations on Clock Skew” , 2014 , APCCAS 2014 , 2014 /11 /17 ~ 2014 /11 /20 , 中華民國 台灣 .
  54. Hao-Wei Liao(廖皓瑋);Shih-Hsu Huang(黃世旭);Hua-Hsih Yeh;Wen-Pin Tu , “Simultaneous Date Path Synthesis and Clock Skew Scheduling for Leakage and Glitch Power Minimization” , 2014 , The 3rd International Symposium on Next-Generation Electronics , 2014 /5 /7 ~ 2014 /5 /10 , 中華民國 台灣 .
  55. Hua-Hsin Yeh;Chen-Yu Huang(黃震宇);Shih-Hsu Huang(黃世旭) , “Temperature Rise Minimization through Simultaneous Layer Assignment and Thermal Through-Silicon-Via Planning” , 2013 , IMPACT-IAAC 2013 , 2013 /10 /22 ~ 2013 /10 /25 , 中華民國 台灣 .
  56. 鄭曜鐘;葉驊昕;?雯斌;黃世旭 , “考慮多重電壓之延遲補償最小化” , 2013 , 2013電子工程技術研討會 , 2013 /5 /24 ~ 2013 /5 /24 , 中華民國 台灣 .
  57. 陳劭恩;張家銘;葉驊昕;?雯斌;黃世旭 , “依據元件庫特性實現低功率時鐘樹之合成方法” , 2013 , 2013電子工程技術研討會 , 2013 /5 /24 ~ 2013 /5 /24 , 中華民國 台灣 .
  58. 王詩集;黃世旭;葉驊昕;程駿華 , “活動導向時鐘閘控制樹峰值電流最小化” , 2012 , ISC 2012 第六屆智慧系統工程應用研討會 , 2012 /5 /3 ~ 2012 /5 /3 , 中華民國 台灣 .
  59. 曾韋碩;程駿華;黃世旭 , “利用三維基體電路堆疊方式選擇使矽晶穿孔數目最小化” , 2012 , ISC 2012 第六屆智慧系統工程應用研討會 , 2012 /5 /3 ~ 2012 /5 /3 , 中華民國 台灣 .
  60. Wen-Pin Tu(?雯斌); Shih-Wei Wu(吳世偉); Sihi-Hsu Huang(黃世旭);Mely Chen Chi(陳美麗) , “NBTI-Aware Dual Threshold Voltage Assignment for Leakage Power Reduction” , 2012 , 2012 IEEE International Symposium on Circuits and Systems (ISCAS)(國際電機電子工程師學會電路與系統國際研討會) , 2012 /5 /20 ~ 2012 /5 /23 , Republic of Korea .
  61. Hua-Hsin Yeh(葉驊昕); Sihi-Hsu Huang(黃世旭); Chun-Hua Cheng(程駿華) , “A Formal Approach to Slack-Driven High-Level Synthesis” , 2012 , 2012 IEEE International Symposium on Circuits and Systems (ISCAS)(國際電機電子工程師學會電路與系統國際研討會) , 2012 /5 /20 ~ 2012 /5 /23 , Republic of Korea .
  62. Wen-Pin Tu(?雯斌); Sihi-Hsu Huang(黃世旭); Chun-Hua Cheng(程駿華) , “Clock Period Minimization with Minimum Area Overhead in High-Level Synthesis of Nonzero Clock Skew Circuits” , 2012 , IEEE Asia and South Pacific Design Automation Conference (國際電機電子工程師學會亞洲與南太平洋設計自動化國際會議) , 2012 /1 /30 ~ 2012 /2 /2 , Australia .
  63. H.H. Yeh;S.H. Huang;K.H. Li , “3D IC Design Partitioning for Temperature Rise Minimization” , 2011 , IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference , 2011 /10 /19 ~ 2011 /10 /21 .
  64. Nikhil Bhalla;Sheng Shian Li; Danny Wen-Yaw Chung , “Multi-Domain Analysis of Silicon Structures for MEMS Based-Sensors” , 2011 , International COMSOL Conference Boston 2011 , 2011 /10 /13 ~ 2011 /10 /15 .
  65. W.P. Tu;Y.H. Lee;S.H. Huang , “TSV Sharing through Multiplexing for TSV Count Minimization in High-Level Synthesis” , 2011 , IEEE International SOC Conference , 2011 /9 /26 ~ 2011 /9 /28 .
  66. 李秉泓;柯明杰;黃世旭 , “插入隔離元件之低功率設計研究” , 2011 , 2011 資訊技術應用及管理研討會 , 2011 /6 /25 ~ 2011 /6 /25 .
  67. Chun-Hua Cheng;Chih-Hsien Kuo;Shih-Hsu Huang , “TSV Number Minimization Using Alternative Paths” , 2011 , 2011 ICICDT , 2011 /5 /2 ~ 2011 /5 /4 .
  68. 李彥勳;黃世旭 , “智慧型進化演算法於時序限制運算排程之應用” , 2011 , 2011第五屆智慧型系統工程應用研討會 , 2011 /5 /4 ~ 2011 /5 /4 .
  69. 柯明杰;黃世旭;張家銘 , “利用元件特性讓老化效應下之時序差異最小化” , 2011 , 2011第五屆智慧型系統工程應用研討會 , 2011 /5 /4 ~ 2011 /5 /4 .
  70. 黃世旭; 王主料; 黃曼玲 , “A Floorplan-Based Power Network Analysis Methodology for System-on-chip Designs” , 2010 , IFIP International Conference on Embedded and Ubiquitous Computing , 2010 ~ 2010 .
  71. 黃偉倫;黃世旭;凃雯斌;卓冠宇;黃琮淯 , “考慮多重電壓之時鐘樹合成方法” , 2010 , 2010電子工程技術研討會 , 2010 ~ 2010 .
  72. 黃世旭; 卓冠宇; 黃偉倫 , “Minimum Buffer Insertions for Clock Period Minimization” , 2010 , IEEE International Symposium on Computer, Communication, Control and Automation (3CA) , 2010 ~ 2010 .
  73. 葉驊昕; 陳美麗; 黃世旭 , “A Design Partitioning Algorithm for Three Dimensional Integrated Circuits” , 2010 , IEEE International Symposium on Computer, Communication, Control and Automation (3CA) , 2010 ~ 2010 .
  74. 李志宏; 黃琮淯; 程駿華; 黃世旭 , “A Post-Processing Approach to Minimize TSV Number for High-Level Synthesis of 3D ICs” , 2010 , IEEE International Symposium on Computer, Communication, Control and Automation (3CA) , 2010 ~ 2010 .
  75. Shih-Hsu Huang;Guan-Yu Jhuo;Wei-Lun Huang , “Minimum Buffer Insertion for Clock Period Minimization” , 2010 , 2010 International Symposium on Computer, Communication, Control and Automation , 2010 /5 /5 ~ 2010 /5 /7 .
  76. Hua-Sin Ye;Mely Chen Chi;Shih-Hsu Huang , “A Design Partitioning Algorithm for Three Dimensional Integrated Circuits” , 2010 , 2010 International Symposium on Computer, Communication, Control and Automation , 2010 /5 /5 ~ 2010 /5 /7 .
  77. Chih-Hung Lee;Tsorng-Yu Huang;Chun-Hua Cheng;Shih-Hsu Huang , “A Post-Processing Approach to Minimize TSV Number for High-Level Synthesis of 3D ICs” , 2010 , 2010 International Symposium on Computer, Communication, Control and Automation , 2010 /5 /5 ~ 2010 /5 /7 .
  78. 黃世旭; 張家銘; 凃雯斌; 潘松濱 , “Critical-PMOS-Aware Clock Tree Design Methodology for Anti-Aging Zero Skew Clock Gating” , 2010 , ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) , 2010 /1 ~ 2010 .
  79. Yalamandala Raghu;Chun-Hua Cheng;Shih-Hsu Huang , “Post-Floorplan Power Distribution Network Design for 3D ICs” , 2009 , 2009 Electronic Technology Symposium , 2010 ~ 2010 .
  80. Jia-Hong Jian; Chun-Hua Cheng; Chia-Ming Chang; Shih-Hsu Huang , “MINIMUM-POWER CLOCK GATING” , 2009 , 2009 International Symposium on Digital Life Technologies , 2009 /5 /28 ~ 2009 /5 /29 .
  81. 葉烝輔; 程駿華; 黃世旭 , “Surge Current Minimization in High-Level Synthesis” , 2009 , IEEE International Symposium on Circuits and Systems (ISCAS) , 2010 ~ 2010 .
  82. 彭偉君;張家銘;黃世旭 , “狀態暫存器之低峰值電流編碼公式化” , 2009 , 2009第二屆積體光機電科技應用與發展學術會議 , 2009 /3 /18 ~ 2009 /3 /18 .
  83. 黃世旭; 程駿華 , “Timing Driven Power Gating in High-Level Synthesis” , 2009 , IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC) , 2010 ~ 2010 .
  84. 程駿華, 黃世旭, 凃雯斌 , “Module Binding for Gated Clock Designs” , 2008 , VLSI Design/CAD Symposium , 2009 ~ 2009 .
  85. 吳世偉, 黃世旭, 潘松濱, 何元凱, 徐文俊, 陳美麗 , “Dual Threshold Voltage Assignment for Low Power” , 2008 , VLSI Design/CAD Symposium , 2009 ~ 2009 .
  86. 張家銘, 黃世旭, 何元凱, 林佳宗, 王信博, 盧育聖 , “Type-Matching Clock Tree for Zero Skew Clock Gating” , 2008 , IEEE/ACM Design Automation Conference , 2009 ~ 2009 .
  87. 顏瑋廷; 黃世旭; 程駿華 , “Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential” , 2007 , IFIP International Workshop on Embedded Software Optimization , 2010 ~ 2010 .
  88. 黃世旭; 林鈺惠; 黃曼玲 , “Utilizing Clock Skew for Timing Reliability Improvement” , 2007 , IEEE TENCON , 2010 ~ 2010 .
  89. 顏瑋廷; 黃世旭; 程駿華 , “Simultaneous Application of Power Management Scheduling and Operation Delay Selection for Peak Power Minimization” , 2007 , International Computer Symposium , 2010 ~ 2010 .
  90. 黃世旭; 程駿華; 張家銘; 聶佑庭 , “Clock Period Minimization with Minimum Delay Insertion” , 2007 , IEEE/ACM Design Automation Conference (DAC) , 2010 ~ 2010 .
  91. 黃世旭, 程駿華, 江忠信, 張家銘 , “Peak Power Minimization through Power Management Scheduling” , 2006 , IEEE Asia and Pacific Conference on Circuits and Systems (APCCAS) , 2007 ~ 2007 .
  92. 黃世旭, 程駿華 , “Operation Scheduling for False Loop Free Circuits” , 2006 , IEEE Asia and Pacific Conference on Circuits and Systems (APCCAS) , 2007 ~ 2007 .
  93. 黃世旭, 張家銘, 聶佑庭 , “State Re-Encoding for Peak Current Minimization” , 2006 , IEEE/ACM International Conference on Computer Aided Design (ICCAD) , 2007 ~ 2007 .
  94. 黃世旭, 程駿華, 江忠信, 張家銘 , “An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management” , 2006 , Joint Conference on Information Sciences , 2006 /10 ~ 2006 /10 .
  95. 黃世旭, 劉時誌, 陳奕融, 賴建元 , “High-Speed Fuzzy Inference Processor Using Active Rules Identification” , 2006 , Joint Conference on Information Sciences , 2007 /10 ~ 2007 /10 .
  96. 黃世旭, 程駿華, 聶佑庭 , 游煒傑 , “Register Binding for Clock Period Minimization” , 2006 , IEEE/ACM Design Automation Conference (DAC) , 2007 ~ 2007 .
  97. 黃世旭, 張家銘, 聶佑庭 , “Fast Multi-Domain Clock Skew Scheduling for Peak Current Reduction” , 2006 , IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC) , 2007 ~ 2007 .
  98. 黃世旭, 聶佑庭, 許聖裕 , “Minimizing Peak Current via Opposite-Phase Clock Tree” , 2005 , IEEE/ACM Design Automation Conference (DAC) , 2007 ~ 2007 .
  99. 黃世旭, 聶佑庭, 呂逢彬 , “Race-Condition-Aware Clock Skew Scheduling” , 2005 , IEEE/ACM Design Automation Conference (DAC) , 2007 ~ 2007 .
  100. K.H. Bai and S.H. Huang , “Architecture for Downlink Base Transmit Station Modulator in WCDMA System” , 2004 , Conference on Electronic Communication and Application , 2004 ~ 2004 .
  101. Y.R. Chen and S.H. Huang , “VLSI Hardware Implementation for Type-2 Fuzzy Logic Controller” , 2004 , Proc. of 13th Automation Technology Conference, CDROM , 2004 ~ 2004 .
  102. S.H. Huang, L.E. Lee and M.L. Huang , “A Special Purpose Content AddressableMemory for Network Packet Classifier” , 2004 , Symposium on Digital Life and Internet Technologies , 2004 ~ 2004 .
  103. Y.R. Chen and S.H,. Huang , “Type-2 Fuzzy Logic Processor with Uncertainties” , 2004 , Conference on Electronic Communication and Application , 2004 ~ 2004 .
  104. K.H. Bai and S.H. Huang , “Downlink Base Transmit Station Modulator in WCDMA System” , 2004 , 2004 IEEE Asia-Pacific Conference on Circuits and Systems , 2004 ~ 2004 .
  105. S.H. Huang and J.Y. Lai , “A High Speed Fuzzy Infernece Processor with Dynamic Analysis and Scheduling Capabilites” , 2004 , 2004 IEEE Asia-Pacific Conference on Circuits and Systems , 2004 ~ 2004 .
  106. F.P. Lu, Y.T. Nieh, S.H. Huang , “Clock Tree Optimization for the Tolerance of Process Variation” , 2004 , VLSI Design/CAD Symposium , 2004 ~ 2004 .
  107. Shih-Hsu Huang, Yow-Tyng Nieh , “Clock Period Minimization of Non-Zero Clock Skew Circuits” , 2003 , IEEE/ACM International Conference on Computer Aided Design (ICCAD) , 2003 /11 ~ 2003 /11 .
  108. 劉時誌 , 賴建元 , 黃世旭 , “具備規則分析技術之高速模糊推論處理器設計” , 2003 , 通信電子科技與應用研討會 , 2003 ~ 2003 .
  109. 黃世旭 , 許益祥 , “A Timing Driven Approach for Crosstalk Minimization in Gridded Channel Routing” , 2002 , IEEE Asia and Pacific Conference on Circuits and Systems , 2002 /12 ~ 2002 /12 .
  110. 黃世旭 , 彭文宏, 賴建元 , “Automatic Synthesis of Fuzzy Systems Based on Trapezoid-Shaped Membership Functions” , 2002 , IEEE Asia and Pacific Conference on Circuits and Systems , 2002 /12 ~ 2002 /12 .
  111. 黃世旭 , 李龍恩 , “A Pipelined Hardware Architecture for Packet Classification” , 2002 , National Symposium on Telecommunications , 2003 ~ 2003 .
  112. 黃世旭 , 賴建元 , “A High-Speed Fuzzy Inference Processor with Dynamic Scheduling Capability” , 2002 , IEEE International Symposium on Intelligent Signal Processing and Communication Systems , 2003 ~ 2003 .
  113. 黃世旭 , 王主料 , “An Effective Floorplan-Based Power Distribution Network Design Methodology Under Reliability Constraints” , 2002 , IEEE International Symposium on Circuits and Systems , 2002 /5 ~ 2002 /5 .
  114. S.H. Huang, M.C. Chi, H.M. Hsiao , “An Effective Low Power Design Methodology Based on Interconnect Prediction” , 2001 , Proc. of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction , 2001 ~ 2001 .
  115. S.H. Huang, J.Y. Lai , “An Efficient Membership Function Representation For High-Resolution Fuzzy Systems” , 2001 , Proc. of the Workshop on the 21st Century Digital Life and Internet Technologies , 2001 ~ 2001 .
  116. SHih-Hsu Huang , “Synthesis and Optimization of False Loop Free Circuits” , 2001 , the 12th VLSI Design/CAD Symposium , 2002 ~ 2002 .
  117. Shih-Hsu Huang, Jian-Yuan Lai , “A High-Speed VLSI Fuzzy Logic Controller with Pipeline Architecture” , 2001 , the 10th IEEE International Conference on Fuzzy Systems , 2002 ~ 2002 .
  118. Shih-Hsu Huang, W.H. Peng, J.Y. Lai , “A Simulated Evolution Algorithm for The Synthesis of Trapezoid-Shaped Membership Functions” , 2001 , National Computer Symposium , 2002 ~ 2002 .
  119. Shih-Hsu Huang, Hsu-Ming Hsiao , “A Practical Methodology for Pre-Layout Interconnect Yield Prediction” , 2001 , the 12th VLSI Design/CAD Symposium , 2002 ~ 2002 .
  120. SHih-Hsu Huang, Jian_Yuan Lai , “A High-Speed VLSI Pipelined Fuzzy Inference Processor” , 2001 , the 12th VLSI Design/CAD Symposium , 2002 ~ 2002 .
  121. Shih-Hsu Huang, Chu-Liao Wang , “An Effective Approach to Design Power/Ground Distribution Networks at the Floorplan Stage” , 2001 , the 12th VLSI Design/CAD Symposium , 2002 ~ 2002 .
  122. Shih-Hsu Huang, Chu-Liao Wang , “An Effective Modeling Technique for the Power Networks of Reused Blocks in a SOC Design” , 2001 , the 12th VLSI Design/CAD Symposium , 2002 ~ 2002 .
  123. M.C. Chi and S.H. Huang , “A Reliable Clock Tree Design Methodology for ASIC Designs” , 2000 , 1st IEEE International Symposium on Quality of Electronic Design , 2000 ~ 2000 .
  124. S.H. Huang and H.M. Hsiao , “An Interconnect-Driven Low Power Design Methodology” , 2000 , Proc. of International Computer Symposium , 2000 ~ 2000 .
  125. S.H. Huang , “A New Scheduling Algorithm for Automatic Synthesis of the Control Blocks of Multi-way Branch Architectures” , 2000 , Proc. of the 11th VLSI Design/CAD Symposium , 2000 ~ 2000 .
  126. 陳美麗,黃世旭 , “A Practical Clock Tree Synthesis Flow” , 1999 , National Computer Symposium , 1999 ~ 1999 .
  127. Mely Chen Chi, C.M.Tseng, C.Y.Lee, S.H.Huang , “A Practical Interconnect Driven ASIC Design Procedure.” , 1998 , The 11th Annual International ASIC Conference , 1998 ~ 1998 .
  128. S.H. Huang, T.Y. Liu, Y.C. Hsu, Y. J. Oyang , “Synthesis of False Loop Free Circuits” , 1995 , ACM/IEEE Asia and South Pacific Design Automation Conference , 1995 ~ 1995 .
  129. S.H. Huang, Y.L. Jeang, C.T. Hwang, Y.C. Hsu, J.F. Wang , “A Tree-Based Scheduling Algorithm for Control-Dominated Circuits” , 1993 , Proc. of the 30th ACM/IEEE Design Automation Conference , 1993 ~ 1993 .
  130. S. H. Huang, C.T. Hwang, Y.C. Hsu, Y. J. Oyang , “A New Approach to Schedule Operations across Nested-ifs and Nested-loops” , 1992 , Proc. of the 25th ACM/IEEE International Symposiumon Microarchitecture , 1992 ~ 1992 .
  131. S.H. Huang, C.T. Hwang, Y.C. Hsu, Y. J. Oyang , “A New Global Scheduling Algorithm for Structured Programs” , 1992 , Proc. of International Conference on Parallel and Distributed Systems , 1992 ~ 1992 .
  132. C.H. Wen, C.Y. Cheng, Y.Y. Kung, C.Y. Chang, S.H. Huang, C.Z. Yang, Y.J. Oyang , “Major Architectural Features of Spectra-II Superscalar Processor” , 1992 , Proc. of International Conference on Parallel and Distributed Systems , 1992 ~ 1992 .
專書
  1. 唐經洲 ; 許永和; 陳璽煌; 林瑞源; 黃其泮; 黃世旭 , 編著者 , “車用 CAN Bus 網路匯流排系統的理論與實務” , 滄海書局 , 2015 , 978-986-363-016-6 .
展演活動
  1. “2015第6屆IIIC國際創新發明競賽” , 2015第6屆IIIC國際創新發明競賽 , 2015 , 中華創新發明學會、俄羅斯阿基米德國際發明協會 , 2015-11-1 ~ 2015-11-30 .
專利
  1. 黃世旭 ; 董哲瑋 , “Multiplication accumulating device and method thereof” , 發明 , 2022 , 美國 , US 11,294,632 B2 (2022.4) .
  2. 黃世旭 ; 董哲瑋 , “乘積累加裝置及其方法” , 發明 , 2020 , 中華民國 台灣 , I696947 (2020.6) .
  3. Yow-Tyng Nieh; Shih-Hsu Huang; Shih-Chieh Chang, Chung-Han Chou , “Clock Tree in Circuit Having a Power-Mode Control Circuit to Determine a First Delay Time and a Second Delay Time” , 發明 , 2016 , 美國 , 9477258 (2016.10) .
  4. 聶佑庭 ;黃世旭 ;張世杰 ;周仲韓 , “在電路中的時脈樹與其合成方法及操作方法” , 發明 , 2016 , 中華民國 台灣 , I544305 (2016.8) .
  5. Yow-Tyng Nieh, Sheng-Yu Hsu, Shih-Hsu Huang, Yeong-Jar Chang , “Opposite-Phase Scheme for Peak Current Reduction” , 2011 , 美國 , 7904874 (2011.3) .
  6. Yow-Tyng Nieh, Shih-Hsu Huang, Chia-Ming Chang , “Method for Controlling Peak Current of A Circuit Having A Plurality of Registers” , 2010 , 美國 , 7739625 (2010.6) .
  7. 聶佑庭; 黃世旭; 張家銘 , “暫存器之峰值電流控制方法” , 2010 , 中華民國 台灣 , I323397 (2010.4) .
  8. 曾大誠,林佳宗,張家銘,黃世旭 , “有限狀態機電路之分解架構” , 2009 , 中華民國 台灣 , I317486 (2009.11) .
  9. Yow-Tyng Nieh; Sheng-Yu Hsu; Shih-Hsu Huang; Yeong-Jar Chang , “Opposite-Phase Scheme for Peak Current Reduction” , 2008 , 美國 , 7352212 (2008.4) .
  10. 聶佑庭; 許聖裕; 黃世旭; 張永嘉 , “使用相反相位時鐘樹以降低峰值電流之裝置及方法” , 2007 , 中華民國 台灣 , 發明第 I 287187 號 (2007.9) .
技術報告
  1. 黃世旭 , “先進電子設計自動化技術研發-子計畫七:適合大型電路之時序重置設計方法(1/3)” , 2004 .
  2. 黃世旭 , “高效能設計之時鐘週期最小化與數位電路最佳化相關問題研究及工具開發(1/2)” , 2004 .
  3. 黃世旭, 劉時誌, 林鈺惠, 張家銘 , “可有效利用時序差異的區域性以提昇電路效能及可靠度之時鐘樹設計流程與自動化工具開發” , 2003 .
  4. 黃世旭,王主料,賴建元,林鈺惠 , “在佈局規劃階段進行電源分佈網路及接地分佈網路之設” , 2002 .
  5. 黃世旭,王主料,彭文宏,張嗣駿 , “考慮接線效應之深次微米晶片設計流程及設計方法” , 2001 .
  6. S.H. Huang , “CCL 0.35um Library User Guide for FLEX Projec” , 2000 .
  7. S.H. Huang , “FLEX Decoder IC Pre-release 審查報告” , 2000 .
  8. J.F. Hsieh, S.H. Huang , “CD-ROM 相關0.6um Library” , 1997 .