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期刊論文
  1. Wei-Kai Cheng; Zih-Ming Yeh; Hsu-Yu Kao; Shih-Hsu Huang , “Cross-Mesh Clock Network Synthesis” , 2023 , Electronics , vol.12 , p.1-21. (SCI期刊)
  2. Hsu-Yu Kao; Shih-Hsu Huang; Wei-Kai Cheng , “Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware Evaluation” , 2022 , Electronics , vol.11 , p.2107-1-2107-17. (Scopus期刊)(SCI期刊)
  3. Wei-Kai Cheng; Xiang-Yi Liu; Hsin-Tzu Wu; Hsin-Yi Pai; Po-Yao Chung , “Reconfigurable Architecture and Dataflow for Memory Traffic Minimization of CNNs Computation” , 2021 , Micromachines , vol.12 , p.1365-1-1365-18. (EI期刊)(Scopus期刊)(SCI期刊)
  4. Wei-Kai Cheng; Po-Yuan Shen; Xin-Lun Li , “Retention-aware DRAM Auto-Refresh Scheme for Energy and Performance Efficiency” , 2019 , Micromachines , vol.10 , p.1-19. (SCI期刊)
  5. Yu-Yin Kuo, Rui-Yu Wang, Wei-Kai Cheng , “Color Balancing for Double Patterning” , 2017 , Journal of Advanced Engineering , vol.12 , p.121-125.
  6. Wei-Kai Cheng; Jui-Hung HUNG; Yi-Hsuan CHIU , “Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering” , 2016 , IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences , vol.E99-A , p.2388-2397. (SCI期刊)
  7. Jui-Hung Hung ; Yu-Cheng Lin ; Wei-Kai Cheng ; Tsai-Ming Hsieh , “Unified Approach for Simultaneous Functional and Timing ECO” , 2016 , IET Circuits, Devices & Systems , vol.10 , p.514-521. (SCI期刊)
  8. Zih-Ming Yeh; Po-Yuan Shen; Wei-Kai Cheng , “Routability-driven Macro Placement” , 2016 , Journal of Advanced Engineering , vol.11 , p.295-300.
  9. Bing-Yi Tang; Cheng-Chieh Tsao; Wei-Kai Cheng , “A Study on Buffer Adjustment for Hybrid Memory Architecture” , 2016 , Journal of Advanced Engineering , vol.11 , p.49-155.
  10. Wei-Kai Cheng;Yen-Heng Ciou; Po-Yuan Shen , “Architecture and Data Migration Methodology for L1 Cache Design with Hybrid SRAM and Volatile STT-RAM Configuration” , 2016 , Microprocessors And Microsystems , vol.42 , p.191-199. (SCI期刊)
  11. Wei-Kai Cheng; Ting-Wei Hsu; Ruey-Yeu Wang , “Segment-Based Task Scheduling for Thermal Optimization of Stacked Memory Architecture” , 2016 , International Journal of Circuits and Electronics , vol.1 , p.39-48.
  12. Wei-Kai Cheng; Po-Han Wu; Yi-Hsuan Chiu , “A Skew-Window based Methodology for Timing Fixing in Multiple Power Modes” , 2015 , Journal of Information Science and Engineering , vol.31 , p.1795-1812. (EI期刊)(SCI期刊)
  13. Wei-Kai Cheng; Jhih-Kai Yang; Pi-Chieh Cheng; Yi-Chieh Huang , “Optimal Tasks Division and Pages Allocation for Hybrid DRAM/PCRAM Memory Architecture” , 2015 , Journal of Advanced Engineering , vol.10 , p.109-116.
  14. Wei-Kai Cheng; Yen-Heng Ciou; Yi-Hsuan Chiu; Yung-Hao Hsu , “A Detailed Placement and Legalization Method for Placement Finishing” , 2015 , Journal of Advanced Engineering , vol.10 , p.57-66.
  15. Wei-Kai Cheng; Tsu-Yun Hsueh; Jui-Hung Hung; Tsai-Ming Hsieh; Mely Chen Chi , “A Methodology for Placement-Aware Partitioning” , 2013 , WSEAS Transactions on Circuits and Systems , vol.12 , p.13-25. (EI期刊)
  16. Wei-Kai Cheng; Youn-Long Lin , “Code Generation of Nested Loops for DSP Processors with Heterogeneous Registers and Structural Pipelining” , 1999 , ACM Transactions on Design Automation of Electronic Systems (TODAES) , vol.3 , p.231-256. (SCI期刊)
研討會論文
  1. Ching-Chao Ku; Wei-Kai Cheng , “A Machine Learning Framework to Predict DRC Violations” , 2023 , 34th VLSI Design/CAD Symposium , 2023 /8 /1 ~ 2023 /8 /4 , 中華民國 台灣 .
  2. Yi-Ting Hsu; Wei-Kai Cheng , “A Machine Learning Technique for Crosstalk Prediction” , 2023 , 34th VLSI Design/CAD Symposium , 2023 /8 /1 ~ 2023 /8 /4 , 中華民國 台灣 .
  3. Yueh-Fan Lo; Wei-Kai Cheng , “Convolutional Neural Network Accelerator for Integrated Winograd and Convolution Computations” , 2023 , IEEE ICCE-TW 2023 , 2023 /7 /17 ~ 2023 /7 /19 , 中華民國 台灣 .
  4. Hsin-Yi Pai Wei-Kai Cheng , “Framework and Quantization Method Design for CIM” , 2023 , IEEE ICCE-TW 2023 , 2023 /7 /17 ~ 2023 /7 /19 , 中華民國 台灣 .
  5. Hsin-Tzu Wu; Hsin-Yi Pai; Wei-Kai Cheng , “Layer-wise Exploration of Synaptic Array and Weight Mapping on Heterogeneous Tile-based RRAM CIM Architecture” , 2022 , 19th International SoC Design Conference , 2022 /10 /19 ~ 2022 /10 /22 , Republic of Korea .
  6. Ming-Wei Chang; Wei-Kai Cheng , “Applying Machine Learning to Custom-fix Timing Violations after Routing” , 2022 , The 33rd VLSI Design/CAD Symposium , 2022 /8 /2 ~ 2022 /8 /5 , 中華民國 台灣 .
  7. Po-Yao Chung; Wei-Kai Cheng , “A Winograd Architecture Design for Edge AI Accelerator” , 2022 , The 33rd VLSI Design/CAD Symposium , 2022 /8 /2 ~ 2022 /8 /5 , 中華民國 台灣 .
  8. Hung-Jie Chen, Chih-Shuan Wu, Wei-Kai Cheng , “Study of Machine Learning Methodology for Static Timing Analysis” , 2021 , The 32rd VLSI Design/CAD Symposium , 2021 /8 /3 ~ 2021 /8 /6 , 中華民國 台灣 .
  9. Tsai-Yu Tsai, Yu-Cheng Lin, Wei-Kai Cheng , “Flexible Buffer Configuration for Memory Traffic Reduction of CNNs with Rapid Test Algorithm” , 2021 , The 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) , 2021 /3 /29 ~ 2021 /3 /30 , Japan .
  10. Wei-Kai Cheng; Yuan-Chih Lo; Hsia-Tsung Wang , “Architecture Design of Overlap-Add FFT on the Convolution Neural Networks” , 2020 , IEEE ICCE-TW , 2020 /9 /28 ~ 2020 /9 /30 , 中華民國 台灣 .
  11. Wei-Kai Cheng, Xiang-Yi Liu, Tsai-Yu Tsai , “Dataflow Design of Overlap-Add FFT on the Convolution Neural Networks” , 2020 , IEEE ICCE-TW , 2020 /9 /28 ~ 2020 /9 /30 , 中華民國 台灣 .
  12. Jui-Hung Hung; Shih-Hsu Huang; Chun-Hua Cheng; Hsu-Yu Kao; Wei-Kai Cheng , “Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers” , 2020 , IEEE VLSI Test Symposium (VTS) , 2020 /4 /27 ~ 2020 /4 /30 , United States .
  13. Hsia-Tsung Wang; Wei-Kai Cheng , “Application of Overlap-Add FFT Algorithm for Computation Reduction of Convolution Neural Networks” , 2019 , The 22nd Workshop on Synthesis And System Integration of Mixed Information technologies , 2019 /10 /21 ~ 2019 /10 /22 , 中華民國 台灣 .
  14. Xiang-Yi Liu, Yuan-Chih Lo, Tsai-Yu Tsai, Wei-Kai Cheng , “Dataflow Exploration Framework for Data Reuse of CNN Computation” , 2019 , The 30th VLSI Design/CAD Symposium , 2019 /8 /6 ~ 2019 /8 /9 , 中華民國 台灣 .
  15. Wei-Kai Cheng; Chih-Shuan Wu , “Machine Learning Techniques for Building and Evaluation of Routability-driven Macro Placement” , 2019 , IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - TAIWAN , 2019 /5 /20 ~ 2019 /5 /22 , 中華民國 台灣 .
  16. Wei-Kai Cheng , “Machine Learning Techniques for Routability-driven Macro Placement of AI Accelerators” , 2019 , 7th Asian Workshop on Smart Sensor Systems , 2019 /3 /24 ~ 2019 /3 /26 , Japan .
  17. Chen-Hsien Lin, Shih-Hsu Huang, Wei-Kai Cheng , “An Effective Approach for Building Low-Power General Activity-Driven Clock Trees” , 2018 , 15th International SoC Design Conference , 2018 /11 /12 ~ 2018 /11 /15 , Republic of Korea .
  18. Wei-Kai Cheng; Jian-Kai Chen; Shih-Hsu Huang , “Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction” , 2018 , 15th International SoC Design Conference , 2018 /11 /12 ~ 2018 /11 /15 , Republic of Korea .
  19. Wei-Kai Cheng; Xin-Lun Li; Jian-Kai Chen , “DRAM Refresh Improvement with Bank Reordering” , 2018 , 7th International Symposium on Next-Generation Electronics , 2018 /5 /7 ~ 2018 /5 /9 , 中華民國 台灣 .
  20. Wei-Kai Cheng, Yu-Yin Guo, Chih-Shuan Wu , “Evaluation of Routability-driven Macro Placement with Machine-Learning Technique” , 2018 , 7th International Symposium on Next-Generation Electronics , 2018 /5 /7 ~ 2018 /5 /9 , 中華民國 台灣 .
  21. Zih-Ming Yeh; Wei-Kai Cheng , “Hybrid Cross Mesh Synthesis with Register Clustering” , 2018 , 21th Workshop on Synthesis And System Integration of Mixed Information technologies , 2018 /3 /26 ~ 2018 /3 /27 , Japan .
  22. Wei-Kai Cheng; Xin-Lun Li; Jian-Kai Chen , “Integration Scheme for Retention-aware DRAM Refresh” , 2017 , IEEE EDSSC , 2017 /10 /18 ~ 2017 /10 /20 , 中華民國 台灣 .
  23. Chin-Ching Tan; Wen-Hsien Chen; Zih-Ming Yeh; Wei-Kai Cheng , “Routability-driven Macro Placement Considering Pins Location” , 2017 , IEEE EDSSC , 2017 /10 /18 ~ 2017 /10 /20 , 中華民國 台灣 .
  24. Hsu-Yu Kao; Yu Lee; Shih-Hsu Huang; Wei-Kai Cheng; Yih-Chih Chou , “An Industrial Design Methodology for The Synthesis of On-Chip-Variation-Aware Top-Level Clock Tree” , 2017 , VLSI Design /CAD Symposium , 2017 /8 /1 ~ 2017 /8 /4 , 中華民國 台灣 .
  25. Wei-Kai Cheng; Pi-Chieh Cheng; Chih-Shuan Wu , “Power-aware Page Allocation of DRAM/PCRAM Memory Architecture” , 2017 , VLSI Design /CAD Symposium , 2017 /8 /1 ~ 2017 /8 /4 , 中華民國 台灣 .
  26. Hsu-Yu Kao; Yu Lee; Shih-Hsu Huang; Wei-Kai Cheng; Yih-Chih Chou , “An Industrial Design Methodology for The Synthesis of OCV-Aware Top-Level Clock Tree” , 2017 , The 6th International Symposium on Next-Generation Electronics , 2017 /5 /23 ~ 2017 /5 /25 , 中華民國 台灣 .
  27. Wei-Kai Cheng; Po-Yuan Shen , “Retention-aware Refresh Techniques for DRAM Refresh Power Reduction” , 2016 , The 20th Workshop on Synthesis And System Integration of Mixed Information technologies , 2016 /10 /24 ~ 2016 /10 /25 , Japan .
  28. Wei-Kai Cheng; Ruey-Yeu Wang; Xin-Lun Li , “3D Architecture Exploration on Thermal Effect of DRAM Refresh” , 2016 , International Microsystems, Packaging, Assembly and Circuits Technology conference , 2016 /10 /26 ~ 2016 /10 /28 , 中華民國 台灣 .
  29. Hsu-Yu Kao; Te-Jui Wang; Shih-Hsu Huang; Wei-Kai Cheng; Yih-Chih Chou , “Top-Level Activity-Driven Clock Tree Synthesis with On-Chip-Variations Considered” , 2016 , 27th VLSI Design/CAD Symposium , 2016 /8 /2 ~ 2016 /8 /5 , 中華民國 台灣 .
  30. Jui-Hung Hung; Yu-Cheng Lin; Wei-Kai Cheng; Tsai-Ming Hsieh , “Logic Difference Minimization based on Spare Cell Consideration” , 2016 , 27th VLSI Design/CAD Symposium , 2016 /8 /2 ~ 2016 /8 /5 , 中華民國 台灣 .
  31. Wei-Kai Cheng; Pi-Chieh Cheng; Xin-Lun Li , “Adaptive Page Allocation of DRAM/PCRAM Hybrid Memory Architecture” , 2016 , 5th International Symposium on Next-Generation Electronics , 2016 /5 /3 ~ 2016 /5 /6 , 中華民國 台灣 .
  32. Te-Jui Wang; Shih-Hsu Huang; Wei-Kai Cheng; Yih-Chih Chou , “Top-Level Activity-Driven Clock Tree Synthesis with Clock Skew Variation Considered” , 2016 , IEEE International Symposium on Circuits And Systems , 2016 /5 /22 ~ 2016 /5 /25 , Canada .
  33. Wei-Kai Cheng; Po-Han Wu , “A Window-based Methodology for ADBs Insertion and Clock Gating Design in Multiple Power Modes” , 2015 , International Symposium on Next-Generation Electronics , 2015 /5 /4 ~ 2015 /5 /6 , 中華民國 台灣 .
  34. Jui-Hung Hung; Yu-Cheng Lin; Wei-Kai Cheng; Tsai-Ming Hsieh , “A Logic Difference Generator with Spare Cells Consideration for ECO Synthesis” , 2015 , International Symposium on Quality Electronic Design , 2015 /3 /2 ~ 2015 /3 /4 , United States .
  35. Wei-Kai Cheng, Yen-Heng Ciou , “A Data Migration Approach for L1 Cache Design with SRAM and Volatile STT-RAM” , 2014 , International Computer Symposium ICS 2014 , 2014 /12 /12 ~ 2014 /12 /14 , 中華民國 台灣 .
  36. Wei-Kai Cheng, Jhih-Kai Yang , “Optimal Page Allocation Approach on The Hybrid DRAM/PCRAM Memory Architecture” , 2014 , 3rd International Symposium on Next-Generation Electronics (ISNE 2014) , 2014 /5 /7 ~ 2014 /5 /10 , 中華民國 台灣 .
  37. Ting-Wei Hsu; Wei-Kai Cheng; Yung-Hao Hsu; Yan-Heng Ciou , “Segment-Based Task Scheduling for Thermal Optimization of 3D Stacked Memory and Processor Architecture” , 2013 , VLSI Design/CAD Symposium 2013 , 2013 /8 /6 ~ 2013 /8 /9 , 中華民國 台灣 .
  38. Wei-Kai Cheng; Ting-Wei Hsu , “Thermal-Aware Task Allocation, Memory Mapping, and Task Scheduling for 3D Stacked Memory and Processor Architecture” , 2013 , IEEE 2013 Tencon-Spring , 2013 /4 /17 ~ 2013 /4 /19 , Australia .
  39. Yi-Chun Yen; Jhih-Kai Yang; Wei-Kai Cheng , “Memory Binding and Layer Assignment for High-Level Synthesis of 3D ICs” , 2012 , Asia Pacific Conference on Circuits and Systems (APCCAS) , 2012 /12 /2 ~ 2012 /12 /5 , 中華民國 台灣 .
  40. Shau-Hua Guo; Po-Han Wu; Wei-Kai Cheng , “Integrating Clock-Gating and ADB Insertion for Timing Fixing in Multi-Voltage Circuit Design” , 2012 , 23rd VLSI Design/CAD Symposium , 2012 /8 /7 ~ 2012 /8 /10 , 中華民國 台灣 .
  41. Ho-Lin Chang; Hsiang-Cheng Lai; Tsu-Yun Hsueh; Wei-Kai Cheng; Mely Chen Chi , “A 3D IC Designs Partitioning Algorithm with Power Consideration” , 2012 , 13th International Symposium on Quality Electronic Design (ISQED) , 2012 /3 /19 ~ 2012 /3 /21 , United States .
  42. Wei-Kai Cheng; Yi-Chun Yen , “A Resource Binding Technique for TSV Number Minimization in High-Level Synthesis of 3D ICs” , 2011 , 13th International Symposium on Integrated Circuits (ISIC) , 2011 /12 /12 ~ 2011 /12 /14 , Republic of Singapore .
  43. Yi-Chun Yen; Wei-Kai Cheng , “A Resource Duplication Technique for TSV Number Minimization in High-Level Synthesis of 3D ICs” , 2011 , 22nd VLSI Design/CAD Symposium , 2011 /8 /2 ~ 2011 /8 /5 , 中華民國 台灣 .
  44. Wei-Kai Cheng; Youn-Long Lin , “DSP Addressing Optimization for Loop Execution on the Auto-Increment/Decrement Architecture” , 1998 , 11th International Symposium on System Synthesis (ISSS) , 1998 /12 /2 ~ 1998 /12 /4 , 中華民國 台灣 .
  45. Wei-Kai Cheng; Youn-Long Lin , “A Transformation-Based Approach for Storage Optimizations” , 1995 , 32nd Conference on Design Automatipn (DAC) , 1995 /6 /12 ~ 1995 /6 /16 , United States .
  46. Wei-Kai Cheng; Youn-Long Lin , “Code Generation for a DSP Processor” , 1994 , 7th International Symposium on High-Level Synthesis , 1994 /5 /18 ~ 1994 /5 /20 , Canada .
專利
  1. Chih-Wei Chen, Wei-Kai Cheng , “Touch Screen Applied to Electronic Apparatus” , 發明 , 2011 , 美國 , US20110025641 (2011.2) .
  2. Yi-Te Yeh, Wei-Kai Cheng , “Touch Panel Interface System Used on Touch Panel, Touch Device, and Method Thereof” , 發明 , 2011 , 美國 , US20110018819 (2011.1) .
技術報告
  1. 鄭維凱;葉懿德 , “FLEX Single Chip (TA58284A) 邏輯設計報告” , 2002 .
  2. 鄭維凱;,施宏澤;葉懿德 , “FLEX Single Chip (TA58284A) 產品目標規格書” , 2002 .
  3. 鄭維凱;,施宏澤;葉懿德 , “FLEX Single Chip (TA58284A) 工程評估報告” , 2002 .
其他
  1. Hua-Hsin Yeh; Wen-Pin Tu; Shih-Hsu Huang; Wei-Kai Cheng , “Design Partitioning for 3D IC” , 2011 .